A 10 bit 120 MS/s SAR ADC Based on a Novel Low Power Switching Strategy
A 10 bit 120 MS/s high speed and low power successive approximation analog-to-digital converter(SAR ADC)was designed.To address the power consumption of the capacitive digital-to-analog converter(CDAC)module,a dual-level high efficiency switch control strategy that maintains common-mode output was proposed,utilizing capacitive splitting technique combined with a C-2C structure.This structure not only reduced the switching power consumption of CDAC but also eliminated the dependence on the intermediate common-mode level during the CDAC switching process,making it suitable for low voltage processes.In terms of improving the speed,ADC used asynchronous logic for acceleration in its control logic.The comparator adopted a fully dynamic high speed structure,which could achieve a working speed of 3 GHz while ensuring accuracy.For CDAC,redundant bits were inserted to reduce the charging time requirements of high order capacitors.The SAR ADC was implemented in a 40 nm CMOS process and operated at a low voltage of 1.1V.Performance simulations were conducted under various process corner conditions.The results show that at a sampling rate of 120 MHz,the effective number of bits(ENOB)is 9.86 bit,the spurious-free dynamic range(SFDR)is 72 dB,the power consumption is 2.1 mW,and the figure of merit(FOM)is 18.9 fJ/(conv·step).
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