A 12 bit Low Power Resistor-String Architecture DAC
A 12-bit 3.4 MHz low power digital-to-analog converter(DAC)chip was designed in a CMOS process by using the segmented resistor string structure.Combining the design indicators of the building time and static performance,the"5+7"segmented structure was determined to realize good differential nonlinearity(DNL)and integral nonlinearity(INL)characteristics under the condition of guaranteeing the build-up speed and taking into account the mismatch of resistors.The post-simulation results show that at a speed of 3.4 MHz,the DNL is 0.14 LSB and the INL is 1 LSB at room temperature,and at-40 to 125 ℃,the DNL is 0.6 LSB and the INL is 2 LSB.It shows a total harmonic distortion(THD)of-84 dB and an extremely low power consumption of 378 pW at 3 V voltage.The layout area is reduced to 1.09 mm×0.91 mm.
digital-to-analog converter(DAC)segmented structurelow power
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