首页|一种级间运放共享的MASH结构Σ-△调制器

一种级间运放共享的MASH结构Σ-△调制器

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基于55 nm CMOS工艺,设计了 一种级间运放共享的级联噪声整形(MASH)结构Σ-△调制器.采用2-2 MASH结构对调制器参数进行了设计.对经典结构的开关电容积分器进行了改进,并应用到调制器电路的设计中,实现了两级调制器之间的运放共享,在达到高精度的同时减少了运放的数量,显著降低了 MASH结构调制器的功耗.仿真结果表明,在3.3 V电源电压下,调制器信噪失真比为111.7 dB,无杂散动态范围为113.6 dB,整体功耗为16.84 mW.
A MASH Structure Interstage Op-Amp Sharing Σ-△ Modulator
A multi-stage noise-shaping(MASH)structure interstage op-amp sharing Σ-△ modulator was designed in a 55 nm CMOS process.A 2-2 MASH structure was used to design the modulator parameters.An improvement had been made to the classical switched-capacitor integrator and applied to the design of the modulator circuit,realizing the sharing of op-amps between the two stages of the modulator,reducing the number of op-amps while achieving high precision,and significantly decreasing the power consumption of the MASH structure modulator.Simulation results show that at a supply voltage of 3.3 V,the modulator have a signal-to-noise-and-distortion ratio of 111.7 dB,a spurious-free dynamic range of 113.6 dB,and a total power consumption of 16.84 mW.

Σ-△ modulatorinterstage op-amp sharingMASHlow power

彭蠡霄、汪东、李振涛、邓欢、龙睿

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湘潭大学物理与光电工程学院,湖南湘潭 411105

湖南毂梁微电子有限公司,长沙 410005

Σ-△调制器 级间运放共享 级联噪声整形 低功耗

湖南省制造业关键产品揭榜挂帅项目

2022GXGG012

2024

微电子学
四川固体电路研究所

微电子学

CSTPCD北大核心
影响因子:0.274
ISSN:1004-3365
年,卷(期):2024.54(1)
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