Design of a Low Power Clock Generator Based on Capacitor Charging and Discharging
A new low power clock generator based on capacitor charging and discharging was designed in SMIC 0.18 μm CMOS process.In order to reduce the frequency fluctuation caused by temperature change,a negative temperature coefficient bias circuit was designed.The traditional duty cycle adjusting circuit was used to adjust the duty cycle of oscillation waveform.The simulation results show that the oscillator can stably output 7.16 MHz at 3.3 V supply voltage,and the system power consumption is 1.411 mW.The power consumption of the ring oscillator is 0.811 mW,and the phase noise is-104.4 dBc/Hz.In the temperature range of-40 ℃-110 ℃,the frequency of the oscillator changes from 7.116 MHz to 7.191 MHz,and the tolerance is within 1.05％.Compared with other clock generators,the circuit has the characteristics of simple structure,low power consumption,and high frequency stability in a wide temperature range.It can meet the working requirements of the chip and provide a stable clock for the chip.
clock generatorring oscillatorduty cycle adjustment circuitlow power consumption
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