一种基于电容充放电的低功耗时钟发生器
Design of a Low Power Clock Generator Based on Capacitor Charging and Discharging
邓家雄 1冯全源1
作者信息
- 1. 西南交通大学微电子研究所,成都 611756
- 折叠
摘要
基于SMIC 0.18 μm CMOS工艺,设计了一种基于电容充放电的新型低功耗时钟发生器.为了减小温度变化引起的频率波动,设计了负温度系数偏置电路.采用了传统的占空比调节电路,可调节振荡波形的占空比.仿真结果显示,在3.3 V电源电压下,该振荡器可以稳定输出7.16 MHz频率的信号,相位噪声为-104.4 dBc/Hz,系统功耗为1.411 mW,其中环形振荡器功耗为0.811 mW.在-40 ℃～110 ℃温度变化范围内,振荡器的频率变化为7.116～7.191 MHz,容差在1.05％以内.同其他时钟发生器相比,该电路具有结构简单、功耗低,以及在宽温度范围内具有较高的频率稳定性等显著特点,能够满足芯片的工作要求,为芯片提供稳定时钟.
Abstract
A new low power clock generator based on capacitor charging and discharging was designed in SMIC 0.18 μm CMOS process.In order to reduce the frequency fluctuation caused by temperature change,a negative temperature coefficient bias circuit was designed.The traditional duty cycle adjusting circuit was used to adjust the duty cycle of oscillation waveform.The simulation results show that the oscillator can stably output 7.16 MHz at 3.3 V supply voltage,and the system power consumption is 1.411 mW.The power consumption of the ring oscillator is 0.811 mW,and the phase noise is-104.4 dBc/Hz.In the temperature range of-40 ℃-110 ℃,the frequency of the oscillator changes from 7.116 MHz to 7.191 MHz,and the tolerance is within 1.05％.Compared with other clock generators,the circuit has the characteristics of simple structure,low power consumption,and high frequency stability in a wide temperature range.It can meet the working requirements of the chip and provide a stable clock for the chip.
关键词
时钟发生器/环形振荡器/占空比调节电路/低功耗Key words
clock generator/ring oscillator/duty cycle adjustment circuit/low power consumption引用本文复制引用
基金项目
国家自然科学基金重大项目(62090012)
国家自然科学基金重大项目(62031016)
国家自然科学基金重大项目(61831017)
中央在川高校院所重大科技成果转化项目(2022ZHCG0114)
四川省科技计划(2023YFG0079)
出版年
2024
NETL
NSTL
万方数据