一种基于分段电阻的低功耗电流舵DAC
Low-Power Current-Steering DAC Based on Segmented Resistors
刘照 1赵俊杰 1钟国强 1徐宁 1杨吉城 1常玉春 1LU Hongbin 2WANG Jiaqi 2LI Zhaohan2
作者信息
- 1. 大连理工大学集成电路学院,辽宁大连 116620
- 2. School of Integrated Circuits,Dalian University of Technology,Dalian,Liaoning 116620,P.R.China
- 折叠
摘要
基于SMIC 180 nm标准CMOS工艺,设计了一款面积仅为320 μm× 150 μm的10 bit分段式电流舵数模转换器(DAC).该设计采用"5+5"式分段,通过电阻实现高位子DAC的量化阶梯,从而减小高位子DAC所需电流.与原始的电阻量化结构相比,改变电流流向,节约了一半的电流源数量.同时通过校准电阻的方式,有效校准了结构中存在的特殊非理想特性.仿真验证结果表明,本分段电流舵DAC微分非线性(DNL)和积分非线性(INL)最大值分别为0.09 LSB和0.34 LSB,无散杂动态范围为64.52 dB,功耗为8.58 mW.与传统结构相比,该结构面积减小约80％,有效减小分段式电流舵DAC的功耗以及面积.
Abstract
An innovative 10-bit segmented current-steering digital-to-analog converter(DAC)was designed through an SMIC 180 nm standard CMOS process,utilizing a minimalistic footprint of 320 μm×150 μm.The"5+5"segmentation architecture achieves a high-position quantization ladder of the DAC through resistors,thus minimizing the total current.Compared with the original resistance quantization structure,this innovative structure alters the current flow direction,conserving half the current sources.Furthermore,the distinct non-ideal characteristics inherent in this novel structure are rectified effectively using a calibration method,traditionally employed in resistor string DACs.Simulation results show that the differential nonlinearity(DNL)and integral nonlinearity(INL)of the DAC are confined to 0.09 and 0.34 LSB,respectively,while achieving a spur-free dynamic range of 64.52 dB and a power consumption of 8.58 mW.Compared with conventional structures,this structure demonstrates an approximate 80％reduction in the area consumption and mitigates the power and area of the segmented current-steering DAC.
关键词
分段式/电流舵DAC/低功耗/校准Key words
segmented/current-steering DAC/low power consumption/calibration引用本文复制引用
基金项目
大连市科技创新项目(2020RT01)
产业基础再造和制造业高质量发展专项(2022)(TC220A04A-49)
出版年
2024
NETL
NSTL
万方数据