一种应用于音频的可重构Σ-Δ连续时间调制器
Reconfigurable Σ-Δ Continuous-Time Modulator for Audio Applications
罗育豪 1韦保林 1岳宏卫1
作者信息
- 1. 桂林电子科技大学广西精密导航技术与应用重点实验室,广西桂林 541004
- 折叠
摘要
基于180 nm CMOS工艺,设计了一种应用于音频领域的可重构前馈式3阶Σ-Δ连续时间调制器.传统Σ-Δ连续时间调制器只有一种工作模式,而该设计利用可重构的积分器使Σ-Δ连续时间调制器具有高精度和低功耗两种工作模式.此外,采用的加法器提前技术减小了调制器功耗,负电阻补偿技术提高了调制器的SNDR,额外环路延时补偿技术提高了调制器的稳定性.仿真结果表明,在20 kHz信号带宽、1.8 V电源电压下,低功耗模式下调制器的SNDR为94.7 dB,功耗为291 μW;高精度模式下调制器的SNDR为108 dB,功耗为436.6 μW.
Abstract
Based on a 180 nm CMOS process,a sigma-delta continuous-time modulator with reconfigurable feedforward third-order operation was designed for audio applications.The traditional sigma-delta continuous time modulator has only one operating mode,but the proposed modulator with the reconfigurable integrator has two operating modes:high-resolution and low-power consumption modes.In addition,summation ahead is used to reduce the power consumption of the modulator,negative-R compensation is used to improve the SNDR of the modulator,and excess loop delay compensation is used to improve the stability of the modulator.With a signal bandwidth of 20 kHz and supply voltage of 1.8 V,the modulator has an SNDR of 94.7 dB and power consumption of 291 μW in the low-power consumption mode and an SNDR of 108 dB and power consumption of 436.6 μW in the high-resolution mode.
关键词
连续时间/可重构/Σ-Δ调制器/高精度Key words
continuous time/reconfigurable/Σ-Δ modulator/high resolution引用本文复制引用
基金项目
国家自然科学基金(12064003)
国家自然科学基金(62364009)
广西自然科学基金(2021JJA170081)
出版年
2024
NETL
NSTL
万方数据