Design of a 5-9.3 GHz Low-Power Broadband Low-Noise Amplifier
A two-stage,low-power,wideband low noise amplifier(LNA)was designed using a 65 nm CMOS process to address the requirements of wireless local area network(WLAN)devices for Wi-Fi 6 and Wi-Fi 6E(5 GHz,6 GHz)applications.The first stage of the circuit adopts a cascode structure,combining the complementary common-source circuits.By incorporating inductor peaking and negative feedback techniques,the input transconductance is enhanced,the noise is reduced,and the bandwidth is expanded,resulting in improved gain flatness.The second stage introduces an auxiliary amplification structure and an inductor peaking technique based on a common-drain buffer,which cancels out the noise from the first-stage common-source transistor and further extends the bandwidth.Both stages employ the proposed self-forward body biasing technique to reduce the circuit's dependency on the power supply voltage.The overall circuit implements dual-current reuse to effectively lower the power consumption.The simulation results demonstrate that the LNA achieves S21 of 17.8±0.1 dB within the frequency range of 5-9.3 GHz,with S11 less than-9 dB,S22 less than-11.9 dB,and NF below 1.34 dB.The overall circuit power consumption is 5.3 mW at a voltage of 0.8 V.
self-forward body biasinglow noise amplifier802.11axWi-Fi 6(E)
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