Design of 56 Gbit/s Low-Power PAM4 SerDes Transmitter with Fractionally-Spaced FFE
A four-level pulse amplitude modulation(PAM4)SerDes transmitter for high-speed inter-chip interconnections was designed using a 65 nm CMOS technology.The entire transmitter comprises most significant bit(MSB)channels,least significant bit(LSB)channels,clock generation paths,feedforward equalization modules,and interface drivers.A latchless parallel-to-serial conversion technique is used to minimize power consumption.A fractional feedforward equalization technique is employed to extend the frequency compensation range beyond the Nyquist frequency to enhance the adaptability of the output signal to the channel.Additionally,a 4∶1 parallel-to-serial converter with pre-charge ability is utilized to mitigate the impact of the charge-extraction effects.Simulation results demonstrate that the designed transmitter achieves a 56 Gbit/s PAM4 output signal at a supply voltage of 1 V,a clear output eye image,a high-linearity of the level mismatch ratio(RLM)of 93.1％,an output swing of 480 mV,and a power consumption of 75 mW.
four-level pulse amplitude modulationlatchless parallel to serial conversionfractional feedforward equalizationhigh linearitySerDes
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