Low Power Sample-and-hold Circuit Based on 0.18 μm CMOS Process
A sample-and-hold circuit for ADC front-end is designed based on 0.18 μm CMOS process in this paper,and the circuit is realized by using a three-stage structure of input buffer-sample switch-output buffer.In order to improve the steadiness of the sampling and holding circuit,the signal feed-through and clock feed-through elimination structures are designed.To improve the frequency response,a passive negative feedback structure is designed and the effect of device parameters on the circuit performance is investigated.Simulation results show that the feedthrough elimination structure designed in this paper can improve the smoothness of the holding state,and the negative feedback can improve the gain by 36 dB.The circuit has a gain of 0 dB,a 3 dB bandwidth of 1 GHz,a SNR of 48 dB,and an ENOB of 7.7 bit at a sampling rate of 800 MS/s and a 122.6 MHz sine wave input.The layout area is 202 μm × 195 μm and the power consumption is 37.22 mW,which achieves the low-power design goal.
analog-to-digital converterCMOS processlow power consumptionsample-hold circuitfeed-through elimination
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