一种CMOS阻抗谱测量电路设计
Design of a CMOS Impedance Spectrum Measuring Circuit
周子超 1马卓 1卓启越 1邹望辉1
作者信息
- 1. 长沙理工大学物理与电子科学学院,长沙 410114
- 折叠
摘要
为了实现待测阻抗实部与虚部的提取,设计了一款基于0.18 μm CMOS工艺的阻抗谱测量电路,其通过频率响应分析法在数字域中进行累乘与累加的操作,从而得到阻抗谱.该阻抗谱测量电路由Δ-Σ调制器和数字抽取滤波器等电路组成.相较于传统阻抗谱检测电路而言,该电路采用无运放Δ-Σ调制器结构,能对电流信号进行直接转换,减少了一个跨阻放大器(TIA)和一个跨导放大器(OTA),极大程度地减小了芯片的功耗和面积.仿真结果表明,在2 MHz的采样时钟下,2 kHz的带宽内,调制器的信噪失真比(SNDR)达到66.5 dB,有效位数(ENOB)达到10.75 bit,当电源电压为1.8 V时,电路功耗低至140 μW.电路的阻抗谱输出与电流呈现良好线性关系.
Abstract
An impedance spectrum measurement circuit based on the 0.18 μm CMOS process is designed to extract the real and imaginary parts of the impedance.This circuit utilizes frequency response analysis in the digital domain to perform multiplication and accumulation operations,resulting in the impedance spectrum.The impedance spectrum measurement circuit consists of a Δ-Σ modulator and a digital extraction filter,among other circuits.Compared with conventional impedance spectrum detection circuits,this circuit employs an opamp-less Δ-Σmodulator structure that enables direct conversion of the current signal,eliminating the need for a trans-impedance amplifier(TIA)and an operational transconductance amplifier(OTA).This significantly reduces power consumption and chip area.Simulation results demonstrate that at a sampling clock of 2 MHz and within a bandwidth of 2 kHz,the modulator achieves a signal-to-noise and distortion ratio(SNDR)of 66.5 dB and an effective number of bits(ENOB)of 10.75 bits.At a power supply voltage of 1.8 V,the power consumption is as low as 140 μW.The impedance spectrum output exhibits a good linear relationship with the current signal.
关键词
阻抗谱/频率响应分析/无运放△-Σ调制器/CMOS工艺/低功耗Key words
impedance spectrum/frequency response analysis/opamp-less Δ-Σ modulator/CMOS process/low power引用本文复制引用
基金项目
湖南省科技创新计划项目(2023GK2036)
湖南省教育厅科学研究项目(23A0260)
出版年
2024
NETL
NSTL
万方数据