Design of a CMOS Impedance Spectrum Measuring Circuit
An impedance spectrum measurement circuit based on the 0.18 μm CMOS process is designed to extract the real and imaginary parts of the impedance.This circuit utilizes frequency response analysis in the digital domain to perform multiplication and accumulation operations,resulting in the impedance spectrum.The impedance spectrum measurement circuit consists of a Δ-Σ modulator and a digital extraction filter,among other circuits.Compared with conventional impedance spectrum detection circuits,this circuit employs an opamp-less Δ-Σmodulator structure that enables direct conversion of the current signal,eliminating the need for a trans-impedance amplifier(TIA)and an operational transconductance amplifier(OTA).This significantly reduces power consumption and chip area.Simulation results demonstrate that at a sampling clock of 2 MHz and within a bandwidth of 2 kHz,the modulator achieves a signal-to-noise and distortion ratio(SNDR)of 66.5 dB and an effective number of bits(ENOB)of 10.75 bits.At a power supply voltage of 1.8 V,the power consumption is as low as 140 μW.The impedance spectrum output exhibits a good linear relationship with the current signal.
impedance spectrumfrequency response analysisopamp-less Δ-Σ modulatorCMOS processlow power
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