Chip Design of a 3.32 mW Broadband Receiver Covering 0.1-2.0 GHz
Based on the TSMC 65 nm CMOS process,this study proposes a circuit of a wideband and low-power ZIF receiver chip.Its working frequency can cover 0.1-2 GHz.The receiver primarily comprises inductorless wideband low-noise amplifiers,passive mixers,and an intermediate frequency filter.In this study,the conventional transimpedance amplifier or active low-pass filter was replaced by an analog inverter to reduce power consumption and avoid using many capacitors and resistors.This also reduced the layout area.The receiver circuit was simulated using Cadence Explore.At a supply voltage of 1.2 V,the channel gain was approximately 57 dB,channel noise figure was about 5.4 dB,third-order input intermodulation point was more than-16.2 dBm,and P1dB was-9.7 dBm@2 GHz.The IF bandwidth was 190 MHz,and the quiescent power consumption of circuit was only 3.32 mW.
LNApassive mixerinverterfilterlow power consumption
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