Design of a 56 Gbit/s PAM-4 SerDes Receiver integrated with DFE and CDR
A 1/4 rate 56 Gbit/s PAM-4 SerDes receiver with a variable-gain amplifier(VGA),continuous-time linear equalizer(CTLE),decision feedback equalizer(DFE),adaptive threshold voltage tracking engine,and reference-less clock and data recovery(CDR)circuit was designed using 65 nm CMOS technology.The VGA adjusts the amplitude of the received signal.The CTLE and two-tap DFE compensate for channel distortion.The threshold voltage tracking technique was adopted to determine the optimum PAM-4 signal decision levels.The reference-less CDR based on transition selection engine generates the best decision clock and reduces clock jitter caused by asymmetric level shifting without an external reference clock.Simulation results show that the receiver achieves an adjustable gain range of 6.75-20.75 dB and compensates for high-frequency attenuation up to 16 dB@14 GHz with a 1.2 V supply voltage,and the peak-to-peak clock jitter extracted by CDR is 7.21 ps under a 16.1 dB@14 GHz channel.For operation at 56 Gbit/s,the power consumption is 227 mW,and the energy efficiency is 4.05 pJ/bit.
PAM-4SerDes receiverdecision feedback equalizerclock and data recoverythreshold voltage tracking
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