一种集成DFE和CDR的56 Gbit/s PAM-4 SerDes接收机设计
Design of a 56 Gbit/s PAM-4 SerDes Receiver integrated with DFE and CDR
郭嘉乐 1张长春 2张翼 1王静1
作者信息
- 1. 南京邮电大学集成电路科学与工程学院,南京 210023
- 2. 南京邮电大学集成电路科学与工程学院,南京 210023;东南大学毫米波国家重点实验室,南京 210096
- 折叠
摘要
基于65 nm CMOS工艺设计了一款1/4速率56 Gbit/s PAM-4 SerDes接收机,该接收机集成了可变增益放大、连续时间线性均衡(CTLE)、判决反馈均衡(DFE)、自适应阈值电压跟踪和无参考时钟数据恢复(CDR)等电路.可变增益放大技术被用来对接收信号进行幅度调节;CTLE和2抽头DFE被用来进行信道畸变补偿;自适应阈值电压跟踪技术用来确定最优的PAM-4信号判决电平;无参考时钟CDR技术则在无外部参考时钟的前提下,被用来产生最佳判决时钟,同时基于边沿检测技术有效降低了 PAM-4信号非对称电平转换引起的时钟抖动.后仿真结果表明,在1.2 V电源电压下,所设计的PAM-4接收机能够实现6.75～20.75 dB的可调增益范围和高达16 dB@14 GHz的信道高频衰减补偿,且在16.1 dB@14 GHz信道下,CDR提取出的7 GHz时钟抖动峰峰值为7.21 ps.工作于56 Gbit/s速率下,接收机功耗为227 mW,能效为4.05 pJ/bit.
Abstract
A 1/4 rate 56 Gbit/s PAM-4 SerDes receiver with a variable-gain amplifier(VGA),continuous-time linear equalizer(CTLE),decision feedback equalizer(DFE),adaptive threshold voltage tracking engine,and reference-less clock and data recovery(CDR)circuit was designed using 65 nm CMOS technology.The VGA adjusts the amplitude of the received signal.The CTLE and two-tap DFE compensate for channel distortion.The threshold voltage tracking technique was adopted to determine the optimum PAM-4 signal decision levels.The reference-less CDR based on transition selection engine generates the best decision clock and reduces clock jitter caused by asymmetric level shifting without an external reference clock.Simulation results show that the receiver achieves an adjustable gain range of 6.75-20.75 dB and compensates for high-frequency attenuation up to 16 dB@14 GHz with a 1.2 V supply voltage,and the peak-to-peak clock jitter extracted by CDR is 7.21 ps under a 16.1 dB@14 GHz channel.For operation at 56 Gbit/s,the power consumption is 227 mW,and the energy efficiency is 4.05 pJ/bit.
关键词
四电平脉冲幅度调制/SerDes接收机/判决反馈均衡器/时钟数据恢复/阈值电压跟踪Key words
PAM-4/SerDes receiver/decision feedback equalizer/clock and data recovery/threshold voltage tracking引用本文复制引用
基金项目
国家自然科学基金资助项目(62174090)
毫米波国家重点实验室开放课题(K202325)
出版年
2024
NETL
NSTL
万方数据