摘 要:针对电流舵DAC高频下因时钟馈通而导致动态性能指标降低的缺点,提出了一种自适应开关限幅单元,通过对摆幅进行限制从而减少了馈通效应,并且结合开关驱动电路改变了栅极控制信号交叉点的位置,降低开关翻转引入的毛刺,提高了无杂散动态范围.采用了CMOS 0.18μm工艺,结合四项开关等其他结构,设计了一种16位1.5 GSPS的电流舵DAC,并对DAC的性能进行了仿真和测试.测试结果表明DAC拥有良好的线性度,在1.5 GSPS采样率和70 M Hz输入频率的情况下,无杂散动态范围(SFDR)为78.59 dB,动态性能良好.
Design of a High-speed and High-resolution Current Steering DAC
This study introduces an adaptive switching limiter unit to address the limitations of the low dynamic performance of the current-rudder DAC due to clock feed-through at high frequencies.By limiting the amplitude of the swing,the feed-through effect is reduced.Combined with a switch drive circuit,the position of the grid control signal crossing point is changed.As a result,the burrs introduced by switch flipping were reduced,and the spurious free dynamic range was improved.A 16-bit 1.5 GSPS current-steering DAC is designed using CMOS 0.18 μm technology combined with a quad-phase switch and other structures,and the performance of the DAC was simulated and tested.The test results showed that the DAC exhibited good linearity,the spurious free dynamic range was 78.59 dB at 1.5 GSPS sampling rate and 70 M Hz input frequency,and the dynamic performance was good.
digital-to-analog converterswitch limitingquad-phase switch structurespurious free dynamic range
万方数据
维普
