采用SMIC 180 nm CM OS工艺,设计了一款低功耗3阶3 bit Delta-Sigma调制器(DSM).该调制器工作于半周期相位,积分器采用共源共栅型悬浮电源动态放大器(FIA)结构,该结构能够有效降低电路功耗,通过使用多位量化器提高信噪比,并采用数据加权平均(DWA)技术抑制调制回路中因匹配单元误差引起的非线性失真.调制器工作于2.5 MHz,信号带宽20 kHz,仿真得到,在1.2 V的电源电压下功耗为113 μW,SNR/SNDR为98.77/98 dB.
Design a Delta-Sigma Modulator Using a Cascoded Floating-inverter-based Dynamic Amplifier
We employed the SMIC 180-nm CMOS process to design a low-power,3rd order,3-bit delta-sigma modulator(DSM).The modulator operated in a half-delay phase.The integrator utilized a cascaded floating-inverter-based dynamic amplifier(FIA)structure,which effectively reduces the power consumption of the circuit.The signal-to-noise ratio was enhanced by using a multi-bit quantizer,and non-linear distortion caused by a unit mismatch in the feedback loop was suppressed using data-weighted averaging(DWA)technology.The modulator operated at 2.5 MHz with a signal bandwidth of 20 kHz.The simulation results showed that the power consumption was 113 μW under a power supply voltage of 1.2 V,and the SN R/SNDR was 98.77/98 dB.
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