High-precision Two-step SAR ADC Design Using Fully Differential Ring Amplifier
This study presents the design of a high-precision successive approximation register analog-to-digital converter(SAR ADC)with a resolution of 18 bits and a sampling rate of 5 MS/s using the 0.18-μm CMOS process.The overall circuit design followed a two-step methodology,employing a fully differential ring amplifier to amplify the residual voltage from the front-end 8-bit capacitive-split ADC.This amplified signal was then further sampled and quantized using a 10-bit bridged-capacitor ADC in the back-end,resulting in highly accurate analog-to-digital conversion.The thesis employed a fully differential ring amplifier,which featured high bandwidth,high gain,and relatively low power consumption.With its low power consumption,the fully differential ring amplifier effectively enhanced the overall circuit accuracy and substantiated the feasibility of the two-step SAR ADC architecture in high-precision SAR ADC designs.Simulation results demonstrated that by operating at a power supply voltage of 3 V and a sampling rate of 5 MS/s,the SAR ADC achieved an effective number of bits(ENOB)of 17.03 bits,with a power consumption of 5.12 mW.Furthermore,it exhibited a spurious-free dynamic range(SFDR)of 107.5 dB and a signal-to-noise and distortion ratio(SNDR)of 104.3 dB.
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维普
