当时钟与数据恢复电路(Clock and Data Recovery,CDR)作为FPGA内嵌的电路模块时,需要具备灵活的应用配置以适应不同协议下的通信需求.根据不同协议对CDR性能指标的要求,通过量化环路带宽、环路延迟及恢复时钟抖动三者之间的关系对CDR电路进行建模,经过数学分析得到电路各部分模块的最佳增益系数作为配置参数.此外通过控制状态机的工作状态切换实现环路的快速锁定机制,极大地降低了环路锁定时间.基于SMIC 28 nm CMOS工艺,设计了一款数据输入范围在1.5 G～12.5 Gbit/s、参数可编程的PI-CDR电路,适用于8 B/10 B、PRBS的数据调制方式.经过后仿测试,电路最大可追踪1 250 × 10-6的频差,环路锁定时间小于151 ns.
Programmable CDR Circuit Design Based on Phase Interpolator
When employed as an embedded circuit module within FPGAs,the clock and data recovery(CDR)system requires versatile application configurations to cater to diverse communication protocols.Addressing specific protocol performance criteria involves modeling the CDR circuit by quantifying the relationships among loop bandwidth,loop delay,and recovery clock jitters.Through mathematical analysis,optimal gain coefficients for each circuit module component were derived and employed as configuration parameters.Furthermore,a fast locking mechanism for the loop was achieved by controlling the state machine,significantly reducing the time required for loop synchronization.Using the SMIC 28 nm CMOS process as a foundation,a programmable PI-CDR circuit was designed with a data input range of 1.5 G-12.5 Gbit/s,suitable for 8 B/10 B and PRBS data modulation.Post-simulation tests demonstrated the ability of the circuit to track frequency differences of up to 1 250×10-6,with a loop lock time of less than 151 ns.
clock and data recovery circuitsloop filtersphase interpolatorsFPGA
万方数据
维普
