Deep Debugging System Design Based on FPGA Prototyping
FPGA prototype validation is a crucial step in chip design,as its application significantly accelerates the overall chip verification speed and reveals system design flaws that are challenging to detect using other validation methods.For debugging FPGA prototype validation systems,the mainstream tool is the integrated logic analyzer,which,however,presents the following issues:substantial consumption of block random access memory resources,low debugging depth,and limited basic triggering methods.In response to these challenges,this study proposes a deep debugging system.In comparison to Xilinx's integrated logic analyzer,the triggering logic expressions of the presented debugging system support various logic combinations,offering flexible triggering settings.Regarding sampling depth,it can reach 400 000 bits,a 205.2％improvement compared with the maximum sampling depth of 131 072 bits of the integrated logic analyzer.In a scenario with a sampling width of 200 bits and sampling depth of 131 072 bits,it only requires the utilization of 10 block random access memory resources on the FPGA,accounting for a mere 1.4％of the integrated logic analyzer's consumption.
deep debuggingprototype verificationfield programmable gate arraysintegrated logic analyzer
万方数据
维普
