首页|一种基于FPGA的实时图像拼接融合算法电路设计

一种基于FPGA的实时图像拼接融合算法电路设计

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图像拼接在全景等领域应用广泛,其关键技术包括图像配准和图像融合两个部分.为了达到低成本和实时处理,往往需要研究图像拼接电路设计,但众多研究集中于图像配准算法,忽视图像融合算法,更不用说专用电路设计.图像配准算法电路以及外设控制器电路由于其复杂性通常会消耗电路中绝大部分资源,因此,图像融合电路的性能和资源利用就成为影响图像拼接系统性能的两个关键因素.为了高效且低资源消耗地实现配准后图像的融合,设计了一种基于贪心算法搜索接缝线的图像融合算法电路,搭建了完整的从图像数据输入到显示输出的验证原型系统.基于Cyclone Ⅳ现场可编辑门阵列(Field Programmable Gate Array,FPGA)器件的综合结果和理论分析表明,提出的电路在保持低资源占用率和显示效果的同时在时钟频率100 MHz下完成两幅486x643的图像融合耗时6.579 5 ms,约为144 FPS,达到了实时性要求,且经过理论换算,处理速率优于3个比较对象.
A real-time image mosaic and fusion circuit design based on FPGA
Image mosaic is broadly applied in many fields such as panorama,whose key technologies include image registration and image fusion.To obtain low-cost and real-time processing,circuit design for image mosaic should be carried out,while most researches focus on image registration and ignore image fusion algorithms,not to say specific circuit design.Normally,image registration algorithm circuit and peripheral controller consume most of chip resources for their complexity.Therefore,the performance and resource utilization of image fusion circuit are two critical factors affecting the performance of the whole image mosaic system.In order to achieve real-time fusion after image registration with high efficiency and low resource utilization,an image fusion algorithm circuit based on greedy algorithm to search for seam is proposed,forming a complete prototype verification test system from image data source to display.The synthesis result based on the Cyclone Ⅳ Field Programmable Gate Array(FPGA)device and theoretical analysis show that the proposed circuit can complete fusion of two 486x643 images at the clock frequency of 100 MHz while maintaining low resource utilization and display effect,which takes 6.579 5 ms,about 144 FPS,meeting the real-time requirements,and the processing rate is better than the three comparison objects through theoretical conversion.

image mosaicimage fusionFPGAdigital integrated circuit

王瑞博、吕子寒、江先阳

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武汉大学物理科学与技术学院,湖北武汉 430072

武汉大学物理国家级实验教学示范中心,湖北武汉 430072

图像拼接 图像融合 现场可编辑门阵列(FPGA) 数字集成电路

国家自然科学基金国家自然科学基金中央高校基本科研业务费专项中央高校基本科研业务费专项湖北省自然科学基金

61072135819717022042017gf00752042019gf00722017CFB721

2024

微电子学与计算机
中国航天科技集团公司第九研究院第七七一研究所

微电子学与计算机

CSTPCD
影响因子:0.431
ISSN:1000-7180
年,卷(期):2024.41(1)
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