首页|基于FPGA的小目标识别分类系统的设计与实现

基于FPGA的小目标识别分类系统的设计与实现

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为了提高小目标识别和分类的实时性,同时降低识别系统的资源消耗,本文提出了一种简易、高效的现场可编程门阵列(Field Programmable Gate Array, FPGA)小目标识别分类系统.该系统首先通过图像预处理消除图像噪点,并采用并行计算提升系统实时性.然后将处理后的图像与模板进行匹配计算得到识别结果,设计的模板匹配电路具有较小的硬件复杂度和较快的处理速度.实验结果表明,本文所提出的识别系统在680x480图像分辨下,可达137.5帧/s的处理速度,实时性强,同时仅消耗了 9个块随机存储器(Block Random Access Memory, BRAM)和2个数字信号处理器(Digital Signal Processor, DSP),硬件资源消耗较少,在处理小目标识别和分类问题上有较好的实用价值.
An efficient FPGA implementation of a real-time multi-class classifier for small target
With the goal of improving real-time performance in recognizing and classifying small targets, and reducing the resource consumption of the recognition system, a simple and efficient Field Programmable Gate Array (FPGA)-based small target recognition and classification scheme is proposed in this paper. First the system through image preprocessing to remove image noise, and use the real-time performance of the parallel computing system. The processed image is then matched to the template to produce the recognition result. The designed template matching circuitry has lower hardware complexity and faster processing speed. The results of the experiment show that the recognition system proposed in this paper can process 137.5 frames at 680x480 image resolution, and has a strong performance in real time. At the same time, it consumes 9 Block Random Access Memory (BRAM) and 2 Digital Signal Processor (DSP), which is of great practical value in small target recognition and classification.

target recognitionclassification systemimage processingFPGAtemplate match

庞宇、杨家斌、王元发、周前能

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重庆邮电大学光电工程学院,重庆 400065

目标识别 分类系统 图像处理 FPGA 模板匹配

国家自然科学基金重庆市自然科学基金重庆市创新小组项目重庆市技术创新与应用发展专项

61971079cstc2021jcyjmsxmX0590cstc2020jcyjcxttX0002cstc2021jscxgksbX0038

2024

微电子学与计算机
中国航天科技集团公司第九研究院第七七一研究所

微电子学与计算机

CSTPCD
影响因子:0.431
ISSN:1000-7180
年,卷(期):2024.41(3)
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