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基于向量表的RISC-V处理器普通中断与NMI优化设计

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针对有实时性需求的精简指令集计算机(Reduced Instruction Set Computer,RISC)-V处理器中断响应延迟过长的问题,本文改进了中断响应中中断服务程序跳转地址计算的方式,扩展了不可屏蔽中断(Non-Maskable Interrupt,NMI)响应时的控制寄存器,提出了硬件矢量中断以及NMI相关控制寄存器扩展.硬件矢量中断提高了中断的响应速度,减少了中断响应的延迟.NMI扩展控制寄存器减少了 NMI的响应延迟,减少了软件需要进行的保存现场操作.利用VCS仿真验证了中断优化的正确性以及性能.仿真结果表明,硬件矢量中断响应时间缩短了 84.4%,响应速度提高为原本的6倍,NMI扩展控制寄存器减少了 31个时钟周期的响应时间以及32个时钟周期的返回时间.
Interrupt and NMI optimization in RISC-V processor based on vector table
In response to the problem of long interrupt response delay in Reduced Instruction Set Computer(RISC)-V processors with real-time requirements,this paper improves the calculation method of the interrupt service program address in interrupt response,extends the Control and Status Register(CSR)during Non-Maskable Interrupt(NMI)response,and proposes hardware vector interrupt and NMI-related CSR extension.The hardware vector interrupt improves the interrupt response speed and reduces the interrupt response delay.The NMI extension control register reduces the response delay of NMI and reduces the need for software to save the context.The correctness and performance of interrupt optimization were verified using VCS simulation.The simulation results show that the response time of hardware vector interrupt is shortened by 84.4%,and the response speed has improved sixfold compared to the original.The NMI extension control register reduces the response time by 31 clock cycles and the return time by 32 clock cycles.

RISC-Vprocessorinterrupt optimizationvector tableCSRNMI

高嘉轩、刘鸿瑾、施博、年嘉伟、高鑫

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北京控制工程研究所,北京 100190

北京轩宇空间科技有限公司,北京 100080

西安电子科技大学计算机科学与技术学院,陕西西安 710071

RISC-V 处理器 中断优化 向量表 控制寄存器 NMI

2024

微电子学与计算机
中国航天科技集团公司第九研究院第七七一研究所

微电子学与计算机

CSTPCD
影响因子:0.431
ISSN:1000-7180
年,卷(期):2024.41(4)
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