微电子学与计算机2024,Vol.41Issue(6) :95-102.DOI:10.19304/J.ISSN1000-7180.2023.0395

高精度电压电流转换电路中电流镜校准技术

Calibration technology of current mirror for high accurate voltage to current converter

王巍 吴浩 丁辉 夏旭 童涛 郭家成 王方 谢应涛
微电子学与计算机2024,Vol.41Issue(6) :95-102.DOI:10.19304/J.ISSN1000-7180.2023.0395

高精度电压电流转换电路中电流镜校准技术

Calibration technology of current mirror for high accurate voltage to current converter

王巍 1吴浩 1丁辉 1夏旭 1童涛 1郭家成 1王方 1谢应涛1
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作者信息

  • 1. 重庆邮电大学 光电学院/国际半导体学院,重庆 400065
  • 折叠

摘要

电流镜输出误差主要由 3 个不同失配源造成:漏源电压(VDS),阈值电压(Vth),跨导系数(β).其中,第一项VDS失配通常是由有限输出阻抗引起的确定性误差,该误差可以通过使用级联结构以及增益提升技术避免,后两项Vth和β失配是由工艺引起的随机性误差.为解决电流镜因工艺失配现象导致的电压电流(Voltage to Current)转换电路精度、线性度较差的问题,提出了一种动态元件匹配(Dynamic Element Match,DEM)以及修调技术(TRIM)相结合的电流镜校准方法,该方法使用TRIM技术将待校准输出电流镜支路和基准电流镜支路之间的误差电流,通过电容与MOS管转换成校准电流后反馈流入待校准输出电流镜支路完成校准,并通过DEM技术切换多条待校准输出电流镜支路完成校准的同时使输出误差平均化.本文采用SMIC 0.18 μm BCD工艺对所提出的V-I转换电路进行了电路设计,仿真结果表明,V-I转换电路的输出电流的失配误差从 0.12%下降到了 0.03%,有效位数ENOB达到了 11.2 bit,总谐波失真THD为-72.6 dB.

Abstract

The output error of the current mirror is mainly caused by three different sources of mismatch:the drain-source voltage(VDS),the threshold voltage(Vth),and the transconductance coefficient(β).The first term VDS mismatch is usually a deterministic error caused by finite output impedance,which can be avoided by using cascade structure and gain boosting technology.The second Vth and third β mismatches are random errors caused by the process.In order to solve the voltage to current converter accuracy and poor linearity,a current mirror calibration method combining Dynamic Element Match(DEM)and TRIM technology is proposed,this method uses TRIM technology to convert the error current between the output current mirror branch to be calibrated and the reference current mirror branch into a calibration current through a capacitor and a MOSFET,and then feedback into the output current mirror branch to be calibrated to complete the calibration,and through DEM technology switch multiple output current mirror branches to be calibrated to complete the calibration and average the output errors at the same time.Based on the SMIC 0.18μm BCD process,the circuit design of the V-I converter using DEM and TRIM technology is completed.The simulation results show that the mismatch error of the output current of the V-I converter drops from 0.12%to 0.03%,the ENOB reaches 11.2 bit,and the THD is-72.6 dB.

关键词

动态元件匹配(DEM)/TRIM技术/V-I变换/电流镜校准

Key words

DEM/TRIM Technique/voltage to current converter/current mirror calibration

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基金项目

重庆市科技局产业化项目(CSTC2018JSZX-CYZTZX0211)

重庆市科技局产业化项目(CSTC2018JSZX-CYZTZX0048)

出版年

2024
微电子学与计算机
中国航天科技集团公司第九研究院第七七一研究所

微电子学与计算机

CSTPCD
影响因子:0.431
ISSN:1000-7180
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