多时钟域的可测试性设计有两种描述片上时钟(On Chip Clock,OCC)行为的方法:时钟控制定义(Clock Control Definition,CCD)和命名捕获过程(Named Capture Procedure,NCP).但这两种方法都存在不足:CCD无法定义复杂的时钟方案和捕获方案;NCP所需的测试向量数目多,运行时间久.有鉴于此,提出了一种合并时钟域NCP方法.合并时钟域NCP提高了对时钟、捕获方案、流程的可控性,弥补了 CCD不可控的不足.实验数据表明,合并时钟域NCP在不影响覆盖率的情况下,为固定型故障(Stuck At Fault,SAF)节省约28％的测试向量数量和22％的运行时间,为跳变延迟型故障(Transition Delay Fault,TDF)节省约18％的测试向量数量和13％的运行时间,提升了测试向量的效率,弥补了 NCP的不足.
Optimization of on-chip clock description based on merged clockdomains
There are two ways to describe the behavior of On Chip Clock(OCC)for testability design in multiple clock domains:Clock Control Definition(CCD)and Named Capture Procedure(NCP).However,these two methods have disadvantages:CCD cannot define complex clock schemes and capture schemes,and NCP requires a large number of test vectors and a long running time.In view of this,a combined clock domain NCP method is proposed.The merged clock domain NCP improves the controllability of the clock,capture scheme and flow,and makes up for the lack of CCD control.The experimental data show that the combined clock domain NCP saves about 28％of test vectors and 22％of running time for Stuck At Fault(SAF)and about 18％of test vectors and 13％of running time for Transition Delay Fault(TDF)without affecting the coverage rate.The efficiency of test vectors is improved to make up for the shortage of NCP.
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