More and more semiconductor companies are adopting a new fault model,the Cell Aware Test(CAT),to improve coverage and low defect rates within library cells.However,CAT uses a large number of Test vectors in the process of Auto Test Pattern Generation(ATPG),and the running time is long,which significantly increases the test cost.In order to optimize CAT,Total Critical Area(TCA)and Named Capture Procedure(NCP)methods are added to the ATPG process,where TCA is sorted according to the type of fault and the most likely location of the fault,and the NCP method is used for the Intellectual Property(IP)under test.IP manages the clock domain,controls the clock,and defines the capture scheme for the IP under test.The results show that CAT combining TCA and the combined clock domain NCP approach achieves the optimization goals of increasing coverage,reducing the number of test vectors,and decreasing runtime.Compared with previous CAT optimization studies,the CAT optimization flow combining TCA and combined clock domain NCP achieves better results in optimizing coverage and test vectors.
cell aware testdesign for testcombined clock domain NCPtotal critical area
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