Design of a 14-bit 80 MS/s pipelined A/D converter
Based on the SMIC 0.18 μm CMOS process,a 14 bit 80 MS/s pipelined A/D converter(ADC)is designed.In order to reduce the overall power consumption of the ADC,a 2.5 bit sample-and-hold-less(SHA-less)structure is adopted to reduce noise and power consumption.Further,an improved op-amp based on a telescopic cascode structure is proposed,which improve the speed and gain of the op-amp with lower power consumption by replica-tail feedback technique and gain-boost technique.Only a dynamic latch is adopted in the comparator to reduce inter-stage delay.A gate-voltage bootstrap switch is also employed to reduce the switch on-resistance and improve the sampling network bandwidth and linearity.The chip test results show that the dynamic parameter performance of the ADC does not differ much when the input signal frequency is 10 MHz and 70 MHz,respectively,under the condition of 1.8 V supply voltage and sampling frequency of 80 MHz.In particular,the signal-to-noise distortion ratio(SNDR)is 72.2 dB,the spurious-free dynamic range(SFDR)is 85.82 dB,the effective number of bits(ENOB)is 11.7 bit,and the quality factor(FoM)is 0.38 pJ·conv-1·step-1 when the input signal frequency is 70 MHz.
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