A timing synchronization architecture for eliminating sampling frequency bias
Aiming at the problem that traditional timing synchronization technology is difficult to meet the high speed communication transmission,this paper proposes a timing synchronization architecture based on arbitrary fraction double resampling to eliminate sampling frequency bias,which can be implemented in FPGA hardware platform through algorithm-level pipelined parallel.The proposed timing synchronization architecture includes timing feedback correction loop and sampling frequency bias feedforward correction loop.Specifically,the timing feedback correction loop is implemented by digital square filter.Sampling frequency offset feedforward correction loop is implemented by sliding window.Firstly,the sampling frequency offset is coarse adjusted by resampling at arbitrary rate,and then the sampling frequency offset correction module is used to complete the fine adjustment of sampling frequency offset.Secondly,through theoretical derivation and analysis,this paper gives the parallel FPGA implementation architecture of each module in timing synchronization architecture.Finally,QPSK signals with 800 MHz carrier frequency and 1×108 symbol/s symbol rate are set in MATLAB and FPGA platforms.The proposed parallel joint timing synchronization architecture is simulated and verified in this paper.The results show that the timing synchronization architecture can make the output result consistent with the ideal non-sampling frequency deviation in MATLAB simulation by eliminating the sampling frequency deviation.
万方数据
维普
