Design and validation of a FLASH memory fault detection algorithm
With the advancement of chip manufacturing processes and increasing logic complexity,the demand for non-volatile storage components has risen.Flash storage components are widely used due to their high stability and cost-effectiveness,and are integrated into chips as intellectual property(IP),which leads to increased time and resource costs for testing chip prototype samples.In order to reduce the testing time of chip samples and improve the fault coverage of Flash faults,a novel Flash fault algorithm is proposed.The algorithm extracts sensitization sequences for different faults in the same part of the Flash memory,replaces part of the content of the March-like algorithm,and adds a small number of read and write operations to meet the requirements of all fault sensitization sequences.This reduces the algorithm steps,allowing Flash storage units to achieve higher testing efficiency and detectable fault types through Automatic Test Equipment(ATE).Experimental results demonstrate that,under consistent memory specifications,the proposed algorithm improves testing efficiency by 28%and 52%compared to March-like pFlash and March-like algorithms,respectively.The fault coverage types are increased by 2 to 3 respectively.
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维普
