Abstract
In the inverter circuit,there exists a specific on-off time in each power transistor.As such,to prevent a short circuit of the two switch devices on the upper and lower bridge arms,a specific dead time must be set in the pulse width modulation(PWM)and the sinusoi-dal pulse width modulation(SPWM)signals.In this paper,an intellectual property(IP)core that can introduce a high-precision dead time of arbitrary length into PWM or SPWM signals of the inverter is designed to increase the precision,convenience and generalization of dead time control,resulting in a boosted control accuracy of up to 10 ns.Moreover,the added Avalon bus enables IP cores to be accessed by the field programmable gate array(FPGA)processor in a standard manner and multiple IP cores of the same class can be easily incorpo-rated.In addition,an application for setting and compensating for dead time in a three-phase inverter based on system on programmable chip(SOPC)technology is presented.With the Nios Ⅱ CPU as its core,the system adopts the mean voltage compensation method to calcu-late the compensation voltage,and performs dead-time compensation in a feed-forward manner.The three dead-time IP cores are con-trolled by Avalon bus.These allow the dead time of three groups of power transistors to be accurately controlled and flexibly adjusted.The system also features the master computer communication function while boasting the advantages of flexible control,high precision and low cost.
基金项目
National Natural Science Foundation of China(61961016)
Natural Science Foundation of Hubei Province(2019CFB593)
PhD Research Start-Up Foundation of Hubei Minzu University(MY2018B08)
NETL
NSTL
维普
万方数据