一种基于低成本FPGA的高速8B／10B编解码器设计
A High Speed 8B/lOB Encoder/Decoder Design Based on Low Cost FPGA
陈章进 1钟国海 1毕卓1
作者信息
摘要
本文基于Altera低成本FPGA设计并实现了一种高速8B／10B编码解码器，编码器和解码器均采用并行流水线设计，可以作为高速串行总线中的编码器和解码器用于保证直流平衡、提高时钟恢复能力等。在Ahera公司软件平台QuartusII上进行的综合和仿真结果表明，将该编解码器应用到基于cycloneIII设计的高速SERDES中，可获得超过1．25Gbps的单通道数据率，能够满足高速串行通信要求。
Abstract
In this paper, a high speed 8B/10B Encoder/Decoder is presented in this paper. The Encoder/Decoder is based on Ahera' s low cost FPGA Cyclone family. The Encoder/Decoder includes parallel pipeline structure. The Encoder/Decoder is applied to the Serializer/Deserializer (SerDes) of high-speed serial bus. The Encoder/Decoder is synthesized and simulated by Quartus II. The syn- thesis and analysis results show the maximum frequency is more than 359MHz. The timing simulation results show the clock frequen- cy is more than 125 MHz. The single channel data rate of serial bus can get to 1.25Gbps. The proposed Eneoder/Decoder can meet the requirements of most hi~h-speed serial bus.
关键词
关键字/8B/10B编码/FPGA/SERDES/串行总线Key words
8B/10B Encoder/Decoder/FPGA/SerDes/Serial Bus引用本文复制引用
基金项目
上海科学技术部项目(09530708600和09ZR1412000)
上海市国际科技合作基金项(09700714000)
出版年
2012
NETL
NSTL
维普
万方数据