首页|基于电感耦合互连的三维集成电路测试方法

基于电感耦合互连的三维集成电路测试方法

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电感耦合互连是一种用于三维芯片堆叠封装的无线互连技术.与硅通孔技术相比,它能以更高的灵活性和更低的成本提供芯片间的高带宽通信.然而,在基于电感耦合互连的多芯片堆叠系统中,由于没有物理连接,芯片的功能测试较为困难.为确保信号传输的正确性和稳定性,还需要对电感耦合信号的传输质量进行测试.本文提出了基于电感耦合互连的三维芯片系统测试方法,包括片内自测、芯片层级自排序、片间互测的自测试以及对电感耦合的传输功率进行自动调优.本方法提高了无线三维芯片的可测试性和可显现性,降低了三维芯片测试成本,并提高了测试效率.
Three-dimensional integrated circuit test method based on inductive coupled interconnection
Inductive coupled interconnect is a wireless technology used for interconnecting three-dimensional chip stack packages.It provides high-bandwidth communication between chips with greater flexibility and lower cost than TSV(through silicon via)technology.However,in multi-chip stacked systems that use inductive coupled interconnection,functional testing of the chips is more difficult due to the absence of physical connections.To ensure the correct and stable signal transmission,it is necessary to test the quality of the signal transmission.This paper proposes a test method for 3D chip systems on inductive coupled interconnection,including on-chip self-test,chip-level self-ordering,inter-chip mutual test,and auto-tuning of the transmission power of inductivel coupling.This method aims to improve the measurability and visibility of the wireless 3D chip,reduce the 3D chip test cost,and improve the test efficiency.

ICinductive coupling3D chip stacking3D NoCmeasurability designinterconnect network

崔洋、熊杰、杨卓、高浩、郑攀、蔡雯雯、邹维、邹雪城、张力

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湖北工业大学理学院 武汉 430068

微电子与集成电路"111"引智基地 武汉 430068

华中科技大学集成电路学院 武汉 430074

集成电路 电感耦合 三维芯片堆叠 三维片上网络 可测试性设计 互联网络

国家自然科学基金项目

62304074

2024

微纳电子与智能制造

微纳电子与智能制造

ISSN:
年,卷(期):2024.6(1)
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