物联网场景下基于半并行结构的极化码译码器设计
Design of Polar Decoder on Semi-parallel Architecture in IoT Scenario
郭晶 1李聪端1
作者信息
- 1. 中山大学电子与通信工程学院,广东深圳 518057
- 折叠
摘要
极化码因能达到容量极限的特性和较低的编译码复杂度而引起了广泛关注.针对资源受限情况下的物联网(Internet of Things,IoT)通信场景提出了一种改进的半并行极化码译码器,采用4 bit译码算法和预计算技术,降低了传统半并行结构所带来的时延,实现较低译码时延和较高硬件资源利用效率.实验结果表明,对于(1 024,512)的极化码,该译码器相比传统的半并行译码器和树形结构的2 bit译码器,时延分别降低了 48.64％和75.19％,处理单元的硬件资源利用率提高了 68.42％和119.35％,硬件资源得到了更高效利用,适用于硬件资源受限的IoT场景.
Abstract
Polar codes have attracted widespread attention due to their capacity-achieving property and low encoding and decoding complexity.An improved semi-parallel polar code decoder is proposed for resource-constrained Internet of Things(IoT)communication scenarios,employing a 4 bit decoding algorithm and pre-computation techniques to reduce latency associated with traditional semi-paral-lel architectures,resulting in low decoding latency and high hardware resource utilization efficiency.Experimental results show that for(1024,512)polar codes,compared to traditional semi-parallel decoders and tree-structured 2 bit decoders,the latency of this decoder is re-duced by 48.64％and 75.19％respectively.The hardware resource utilization rate of processing element is increased by 68.42％and 119.35％.The hardware resources are utilized more efficiently,suitable for hardware-constrained IoT scenarios.
关键词
极化码译码/无线通信/物联网应用/硬件结构Key words
polar decoding/wireless communication/applications of IoT/hardware architecture引用本文复制引用
出版年
2024
国家科技期刊平台
NSTL
万方数据