Design and implementation of ultra high-speed IPSec security device based on high performance FPGA
A design scheme for an ultra high speed IPSec security device based on high-performance FPGA has been proposed.On the basis of using CPU as the control center,this scheme utilizes high-performance FPGA combined with high-speed interface to achieve 100G IPSec secure transmission,while utilizing high-performance FPGA and noise source chip to implement national security algorithm for encryption and decryption of high-speed data.Building a testing environment to test the prototype,the test results indicate that,the ultra high speed IPSec security device can achieve IPSec secure transmission with a throughput of up to 82 Gb/s,and the entire system latency can reach 90 μs level.
万方数据
维普
