A parallel cyclic redundancy code(CRC)calculation method is designed and implemented for the CRC calculation circuits in case of high bit-width data,which has the problems of low calcu-lation working frequency and excessive resource consumption.The method splits the CRC calcula-tion into two parts:the data CRC calculation and the remainder CRC calculation.The remainder CRC calculation is accomplished by multiple remainder CRC calculation modules connected in cas-cade,and the data CRC calculation module is realized by a fixed logic expression,and the results of the two calculations are obtained by doing the modulo-two addition.The combination of data CRC calculation module and residue CRC calculation module can be selected by data length to adapt to the CRC calculation of variable data length with high bit width.Taking the CRC-32 calculation of 1 024 bits data in 100 Gbps remote direct memory access(RDMA)communication system as an ex-ample,the hardware circuit of the algorithm is realized on the VCU118 development board.The ex-perimental results show that the proposed design uses only 4 760 lookup tables and 2 658 flip-flops,and the whole system bandwidth can reach up to 97.85 Gbps,and the maximum operating frequen-cy can reach up to 326 MHz.Compared with other related methods,the proposed method has a higher operating frequency and less resource consumption.
high speed communication systemcyclic redundancy check codeparallel CRC splitting calculationhigh bit widthRDMA
NETL
NSTL
维普
万方数据
