To address the issue of low precision in classical noise-shaping(NS)successive approxi-mation register(SAR)analog-to-digital converters(ADCs),a third-order NS-SAR ADC design method combining a dynamic amplifier and an infinite impulse response(IIR)filter is proposed.The precision of the NS-SAR ADC is improved by compensating for the loss of residual voltage through dynamic amplifier gain and IIR filter integral.Meanwhile,the robustness is enhanced by using a floating inverter amplifier(FIA).The ADC is designed in a 0.18 μm CMOS technology,achieving an effective numbers of bits(ENOB)greater than 4.3 bits at a 10 bits circuit structure while con-sidering process-voltage-temperature variations;At a power supply of 1.8 V,a oversampling rate(OSR)of 8 and a sampling rate of 2 kS/s,the signal-to-noise-distortion ratio is 88.2 dB and the power consumption is 1.05 μW,resulting in a Schreier figure-of-merit(FoMs)of 168.9 dB.Com-pared with the classical NS-SAR ADC design,the proposed design achieves higher ADC precision.
analog-to-digital converternoise shapingdynamic amplifierinfinite impulse responseresidual voltage
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