三维集成电路测试方法
Survey on Testing Methods for 3D IC
于淑华 1李凌霞 1邵晶波2
作者信息
- 1. 哈尔滨金融学院计算机系，哈尔滨 150030
- 2. 哈尔滨师范大学计算机科学与信息工程学院，哈尔滨 150025
- 折叠
摘要
制造技术的不断发展使集成电路工业已达到深亚微米级，以TSV技术为基础的三维集成电路解决了器件间互连线长度过长的问题，成为一种具有众多优势极具竞争力的技术。综述基于TSV的三维集成电路测试的新特点，阐述以TSV技术为中心的三维IC的优势，介绍适用于三维IC的测试方法，分类阐述实现此种新技术所需要解决的难题。
Abstract
The rapid development of manufacturing technology has made it possible for semiconductor industry to enter the era of Very Deep Sub-Micron. TSV technology based 3D IC overcome the difficulties of over-long interconnect between each components of IC, therefore becoming an emerging and competitive technique and gains popularity among researchers and developers in related work of line. Overviews the new characteristics of testing and for TSV centered 3D IC, introduces the advantages of 3D IC, and expounds various challenging problems confronted by researchers. Analyses the testing methods suitable for 3D IC and the challenges that must be tackled by the researchers are elaborated in detail.
关键词
三维系统芯片/测试/形式验证/深亚微米/垂直硅通孔Key words
3D IC/Test/Formal Verification/VDSM(Very Deep Sub-Micron)/TSV引用本文复制引用
基金项目
黑龙江省教育厅科技项目(12531183)
出版年
2015
NETL
NSTL
维普
万方数据