Design and implementation of FPGA-based semantic segmentation algorithm
To address the intricacies and real-time imperatives inherent in water surface detection within edge water resources monitoring scenarios,enhancements are made to the BiSeNet network,yielding a streamlined real-time semantic segmentation algo-rithm tailored for FPGA edge devices.This algorithm first undergoes model quantization via Vitis AI,followed by collaborative opti-mization design on the Vitis software platform,leading to the customization of a Deep Learning Processing Unit(DPU)for facilitat-ing the deployment of the semantic segmentation algorithm on FPGA.Evaluation on a proprietary water resources dataset demon-strates the algorithm's ability to maintain commendable performance while incurring only a nominal loss in accuracy.Experimental findings reveal that the refined network model attains an inference speed of 31.06 frames per second(FPS)on the ZCU104 device,with a marginal accuracy decrement of 3.7%.This translates to an inference acceleration of 18.9 times compared to ARM devices.In summary,the proposed methodology satisfies the real-time segmentation requisites of water resources monitoring tasks within low-power constraints.
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