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带狄拉克源的超低功耗负电容晶体管研究

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由于电子/空穴随能量的分布受玻尔兹曼限制,场效应晶体管在室温下的亚阈值摆幅(SS)无法低于60 mV·dec-1,这使得晶体管的功耗无法进一步减小.而狄拉克源晶体管和负电容晶体管分别通过不同的方式实现了低于60 mV·dec-1的陡峭SS,为降低晶体管功耗提供了新的途径.该文首次在实验上将两个物理过程结合起来,实现了带狄拉克源端的超低功耗负电容晶体管.所制备的器件实现了低于60 mV·dec-1的陡峭SS,开态电流能够达到10μA量级,关态电流低于0.1 pA,整体的电流开关比超过8个数量级,器件的栅极电容匹配良好且回滞可忽略.该工作为超低功耗电子器件领域提供了新的可能.
Research on ultra-low power negative-capacitance transistor with Dirac-source
Due to the Boltzmann distribution of electrons/holes,the subthreshold swing(SS)of field effect transistors cannot be lower than 60 mV·dec-1 at room temperature,which prevents further reduction of transistor power consumption.The Dirac-source transistor and negative-capacitance transistor have achieved steep SS below 60 mV·dec-1 in different mechanisms,providing a new way to reduce transistor power consumption.In this article,for the first time,we combine the two physical processes in experiments,and demonstrate the ultra-low power negative-capacitance transistor with Dirac-source.The prepared device can achieve a steep subthreshold swing below 60 mV·dec-1,an ON state current of 10 μA,an OFF state cur-rent below 0.1 pA,and the overall current switching ratio exceeds 8 orders of magnitude.And the gate ca-pacitance of the device is well-matched,with only negligible hysteresis occurring.This work provides new possibilities for the field of ultra-low power electronic devices.

two-dimensional materialsnegative-capacitance transistorDirac-source transistorultra-low power consumptionsubthreshold swing

全辉、曹觉先、肖化平、邱晨光

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湘潭大学湖南先进传感与信息技术创新研究院,湖南湘潭 411105

湘潭大学物理与光电工程学院,湖南湘潭 411105

北京大学电子学院纳米器件物理与化学重点实验室及碳基电子中心,北京 100871

二维材料 负电容晶体管 狄拉克源晶体管 超低功耗 亚阈值摆幅

国家自然科学基金面上项目

61971009

2024

湘潭大学学报(自然科学版)
湘潭大学

湘潭大学学报(自然科学版)

CSTPCD
影响因子:0.403
ISSN:2096-644X
年,卷(期):2024.46(5)