动态双频跳频电台接收端FPGA设计
Design of the receiver of dynamic dual frequency hopping radio based on FPGA
张凤娟 1刘长水 2徐琨1
作者信息
- 1. 湖南机电职业技术学院,长沙 410151
- 2. 国防科技大学智能科学学院,长沙 410005
- 折叠
摘要
为解决动态双频跳频电台跳频信号解跳频这一关键技术的硬件实现,依照动态双频跳频同步方案,设计了跳频电台接收端的整体结构,研究了跳频电台接收端解跳频的数学模型,采用Verilog HDL语言在EP4CE6F17C8芯片上实现了两种解跳频器设计方案,分别为IP核乘法器解混频+带通滤波+BPSK解调方案和加法树乘法器解混频+带通滤波+改进型DPSK解调方案.测试结果表明,两种方案都能实现跳频电台接收端解跳频器功能,后一方案消耗硬件资源更少,更符合跳频电台接收端多通道并行运算要求,为下一步研制动态双频跳频电台样机提供了技术参考.
Abstract
In order to solve the hardware implementation of frequency hopping signal de-hopping which is the key technology of dynamic dual-frequency frequency hopping radio,according to the dynamic dual fre-quency hopping synchronization scheme,the overall structure of the receiver of the frequency hopping radio station is designed,and the mathematical model of de-frequency hopping at the receiver of the frequency hopping radio station is studied.Two design schemes of de-frequency hoppers are realized on EP4CE6-F17C8 chip by using Verilog HDL language,which are IP core multiplier de mixing+band-pass filtering+BPSK demodulation scheme and adder tree multiplier de mixing+band-pass filtering+improved DPSK demodulation scheme.The test results show that both schemes can realize the function of de-frequen-cy hopping at the receiver of frequency hopping radio.The latter scheme consumes less hardware resources and better met the requirements of multi-channel parallel operation at the receiver of frequency hopping ra-dio,which provides a technical reference for the further development of dynamic dual frequency hopping ra-dio prototype.
关键词
动态双频跳频/跳频电台/跳频接收机/解跳频器/现场可编程门阵列Key words
dynamic dual frequency hopping/frequency hopping radio/frequency hopping receiver/de-frequency hoppers/field-programmable gate array引用本文复制引用
基金项目
湖南省自然科学基金-科教联合项目(2020JJ7003)
湖南省教育厅科学研究项目(20C0705)
出版年
2024
NETL
NSTL
万方数据