Design of the receiver of dynamic dual frequency hopping radio based on FPGA
In order to solve the hardware implementation of frequency hopping signal de-hopping which is the key technology of dynamic dual-frequency frequency hopping radio,according to the dynamic dual fre-quency hopping synchronization scheme,the overall structure of the receiver of the frequency hopping radio station is designed,and the mathematical model of de-frequency hopping at the receiver of the frequency hopping radio station is studied.Two design schemes of de-frequency hoppers are realized on EP4CE6-F17C8 chip by using Verilog HDL language,which are IP core multiplier de mixing+band-pass filtering+BPSK demodulation scheme and adder tree multiplier de mixing+band-pass filtering+improved DPSK demodulation scheme.The test results show that both schemes can realize the function of de-frequen-cy hopping at the receiver of frequency hopping radio.The latter scheme consumes less hardware resources and better met the requirements of multi-channel parallel operation at the receiver of frequency hopping ra-dio,which provides a technical reference for the further development of dynamic dual frequency hopping ra-dio prototype.
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