A digital pixel focal plane readout circuit with integrated image processing function
A pixel-level digital focal plane readout circuit was designed to overcome the charge capacity limitations of traditional analog readout circuit technology,enabling a larger dynamic range and lower noise digital image readout.Additionally,digital image processing is performed internally at the pixel level,enabling functions such as Non-Uniformity Correction(NUC),dead pixel compensation,digital Time-Delay Integration(TDI),and spatial filtering for image preprocessing.The circuit was fabricated using a 40 nm CMOS process with an array specification of 640×512,a pixel pitch of 30 μm,and the overall chip size is approximately 22 mm×19 mm.Test results indicate that the circuit can significantly reduce(by approximately 90%and 63%,respectively)the spatial noise in the output image through TDI and spatial filtering functions,thereby enhancing the image quality.
万方数据
维普
