Research Progress on Near-Edge Geometry of Silicon Wafer:A Review
Near-edge site flatness was constantly focused upon to meet the near-edge yield demand of integrated circuit.Especially,as for the developments of high frequency and low power dissipation device,bonding become an advanced technical to silicon-on-insu-lator(SOI)manufacture,which challenged the near-edge geometry of silicon wafer.The knowledge of research progress on near-edge geometry is conducive to the localization of silicon wafer.This paper mainly analysised the existed researches on silicon wafer near-edge geometry from Semiconductor Equipment and Materials International(SEMI)standards,literature and patents.Four SEMI stan-dards quantified the near-edge geometry of silicon wafer,and ruled the metrics related to the edge roll off,near-edge curvature and near-edge flatness of silicon wafer.SEMI M77-1110 introduced the practice for determining the near-edge geometry using roll off amount(ROA),which was the difference of prediction value and actual measuring result.The prediction method in SEMI M77 con-tained linear reference and polynomial reference,SEMI M68-0315 introduced the practice for determining the near-edge geometry from a measured height data array using a curvature metrics,in which a double derivative on height(ZDD)along radial direction was subjected.SEMI M67-1109 was a practice for determining the near-edge geometry using partial wafer site flatness,in which a serious of variations base on different reference plane was subjected,namely,ESFQR,ESFQD and ESBIR.The selection of near-edge geome-try standards based on the consideration of applications,site flatness parameters were key parameters for integrated circuits,while ZDD and ROA would be necessary parameters on bonding usages.The actual test methods were also developed to meet the standards.For instance,a stylus profiler and a block gauge had been applied to measure the profile of a near-edge region of wafer.The test meth-ods and process control of near-edge micro-roughness were also studied,atomic force microscope(AFM),interferometer and scat-terometer were commonly used in practice field.From literature,site flatness control and improvement had always been focused ever since the beginning of silicon wafer industry,300 mm wafer near-edge geometry started to be learned when SOI became an indispens-able solution.For the aspect of site flatness,the polishing method(single side polish and double side polish),cost materials such as slurry and pad,process parameters of polishing such as pressure,slurry concentration and rotation speed were studied.In terms of pol-ishing process parameters,pressure,the relative speed of the polishing head and the polishing disk,the slurry flow rate and the pol-ishing time could affect the near-edge site flatness of the silicon wafer.Especially,as for most 200 mm wafer was single side polished,some pre-polish handling methods were learned to improve the post-polish site flatness qualities.For near-edge geometry,most at-tempts were to find solutions to control ROA and ZDD of double side polish based on 300 mm silicon wafer manufacture environment,a various of polishing pads were designed and evaluated,a double-layered polishing pad and a new three-layered polishing pad were proved to reduce ROA,some water-soluble polymer could improve the near-edge geometry,the key character of regular polishing pad on near-edge geometry were also quantified.In addition,the contribution of grinding and etching were detected and experiments were carried out to maintain the near-edge geometry of 300 mm silicon wafer.This paper mainly researched ZDD and ROA related patents,which found process flow adjustments and new process methods were the key.There were two patents were considered to be foundation-al:One patent introduced a 2-step front side grinding between etching and polishing,which removed the mounds,dimples and other geometry defects at the same time produced a flat near-edge geometry,the post-bonding edge defect was significantly improved.The other patent adjusted the grinding tool and grinding process parameters,to form a special wafer shape,which had a sag formed at an outer periphery while the center of the wafer had a convex shape,this special pre-polishing shape produced several near-edge geometry parameters at the same time,namely ESFQR,ROA and ZDD.300 mm silicon polished substrate and SOI used wafer were mature pro-ductions in semiconductor industry,which had been already configurated with international standards,adequate research findings and patents.Due to the rapid market demand of 5G devices and portable equipment,200 mm SOI wafer would take considerable market share,which would drive more research on near-edge geometry.Besides,the silicon-based compound semiconductor was gradually ris-ing in recent years due to the application of bonding technical,the near-edge geometry research of small size silicon wafer and com-pound semiconductor wafer would also be foreseeable.
edge roll off(ERO)near-edge curvaturenear-edge flatnessbonding
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