Optimization of EtherCAT Distributed Clock Drift Compensation Based on PI Closed-loop Feedback
The application of industrial buses in various fields is becoming increasingly important,but the increase in devices connected to the bus can lead to synchronization issues such as high latency.This article conducts research and analysis on dis-tributed clock synchronization algorithms based on EtherCAT.In response to the problem of low compensation accuracy in the drift compensation process,a dynamic drift compensation algorithm based on closed-loop feedback control was proposed.The algorithm first improves the local clock by using fixed point numbers,and then uses PI algorithm to adjust the drift compensation value.Fi-nally,a testing platform was built,including a master station based on SOEM implementation and a slave station based on STM32+FPGA architecture.The optimized algorithms were implemented in FPGA before and after optimization.The test results show that the local clock resolution improved by fixed point number can reach 2-20 ns,and the drift compensation algorithm optimized by PI closed-loop feedback can reduce the synchronization error to within 25 ns,significantly improving the synchronization per-formance between slave stations.
EtherCATclock synchronizationdrift compensationdistributed clockFPGAPI control
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