基于PI闭环反馈的EtherCAT分布式时钟漂移补偿优化
Optimization of EtherCAT Distributed Clock Drift Compensation Based on PI Closed-loop Feedback
张恩源 1李松 2张黎明 2郭凯 2赵鹏3
作者信息
- 1. 沈阳理工大学自动化与电气工程学院;中国科学院沈阳自动化研究所机器人学国家重点实验室;中国科学院机器人与智能制造创新研究院
- 2. 中国科学院沈阳自动化研究所机器人学国家重点实验室;中国科学院机器人与智能制造创新研究院
- 3. 中国科学院沈阳自动化研究所机器人学国家重点实验室;中国科学院机器人与智能制造创新研究院;沈阳理工大学机械工程学院
- 折叠
摘要
接入工业总线的设备的增加会导致高延迟等同步性问题.基于EtherCAT对分布式时钟同步算法进行研究与分析,针对其在漂移补偿过程中存在补偿精度低的问题,提出了一种基于闭环反馈控制思想的动态漂移补偿算法.算法先利用定点数改进本地时钟,再利用PI控制调节漂移补偿值.最后搭建了测试平台,包括基于SOEM实现的主站与基于STM32+FPGA架构实现的从站,优化前后的算法分别在FPGA中实现.测试结果表明:定点数改进的本地时钟分辨率可以达到2-20 ns,PI闭环反馈优化后的漂移补偿算法可以将同步误差降低到25 ns之内,明显提高从站之间的同步性能.
Abstract
The application of industrial buses in various fields is becoming increasingly important,but the increase in devices connected to the bus can lead to synchronization issues such as high latency.This article conducts research and analysis on dis-tributed clock synchronization algorithms based on EtherCAT.In response to the problem of low compensation accuracy in the drift compensation process,a dynamic drift compensation algorithm based on closed-loop feedback control was proposed.The algorithm first improves the local clock by using fixed point numbers,and then uses PI algorithm to adjust the drift compensation value.Fi-nally,a testing platform was built,including a master station based on SOEM implementation and a slave station based on STM32+FPGA architecture.The optimized algorithms were implemented in FPGA before and after optimization.The test results show that the local clock resolution improved by fixed point number can reach 2-20 ns,and the drift compensation algorithm optimized by PI closed-loop feedback can reduce the synchronization error to within 25 ns,significantly improving the synchronization per-formance between slave stations.
关键词
EtherCAT/时钟同步/漂移补偿/分布时钟/FPGA/PI控制Key words
EtherCAT/clock synchronization/drift compensation/distributed clock/FPGA/PI control引用本文复制引用
基金项目
基础加强计划技术领域基金项目(2021-JCJQ-JJ-1088)
国家自然科学基金青年项目(52205319)
出版年
2024
NETL
NSTL
万方数据