Analysis of Time Delay Characteristics of Petri Nets Based on Coarse Grained Reconfigurable Architecture Mapping
Aiming at the mapping problem of data flow graph of coarse-grained reconfigurable computing array under multiple con-straints,the time Petri net is analyzed and modeled,and two algorithms,width mapping and width greedy mapping,are proposed.These two algorithms are tested based on a set of experimental benchmarks and randomly selected processing unit arrays PEA4×4 and PEA5×5.The results show that compared with the width mapping algorithm,the width greedy mapping algorithm is opti-mized in the number of mapping blocks,execution delay,input and output memory access costs,and the average total delay is re-duced by 24.5%.
Petri nettime delay characteristics analysiscoarse grained reconfigurable architecturemapping
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