Design of Low-jitter Charge Pump Phase-locked Loop and Modeling Simulation in Simulink
With the advancement of integrated circuit technology,the working frequency of circuits is becoming higher and higher,which also puts forward higher requirements for clock signal jitter and phase noise.In response to the problems of multiple parameters,complex structure,and long transient simulation time in the phase-locked loop circuit,a mathematical model of the charge pump phase-locked loop system is established,and MATLAB/Simulink is used to model the negative feedback system,achieving rapid dynamic simulation of the charge pump phase-locked loop.The circuit design,layout,physical verification,and extraction of parasitic pa-rameters and post-simulation of the phase-locked loop were completed,and a low jitter charge pump phase-locked loop with a typical value of input frequency of 30 MHz and a locking frequency of 1.5 GHz was designed in TSMC 65 nm CMOS process.The post-simulation results show that the PLL circuit has a good performance in-dex,under typical value,the PLL has a lock-up time of 10 μs,peak-to-peak jitter of 2.68 ps during lockup,a clock signal duty cycle of 45％.
phase-locked loopphase frequency detectorcharge pumpvoltage-controlled oscillator
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