Design of Highly Efficient RS Encoder and Decoder Based on High-speed Memory Platform
Commercial IP core is currently used in the development of high-speed memory device to achieve date error correc-tion,the maximum achievable encoding and decoding speed is 800Mbps,which can only rely on multiple IP cores working simulta-neously to meet the requirements of gigabit high-speed data access rate.In view of the bit error characteristics of spaceborne storage data,this paper proposes an improved RS decoding algorithm,which reduces the number of iterations and the amount of computa-tion in the decoding process by downgrading the residual polynomial in the encoding algorithm and the syndrome polynomial in the decoding algorithm,and adopts the sub-term multiplexing technology for the finite field multiplier of the basic operation unit in the decoding algorithm.The implementation results indicate that the maximum speed the encoder and decoder can achieve 10.5 Gbps,while the encoder resources is reduced by 15%and decoder resources reduced by 40%compared to a single commercial IP core,which can meet the application needs of high-speed of memory platform.
High-speed of memory platformRS encoder and decoderData error correction
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