首页|Low Overhead and Fast Reaction Adaptive Clocking System for Voltage Droop Tolerance
Low Overhead and Fast Reaction Adaptive Clocking System for Voltage Droop Tolerance
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维普
Variation in on-chip power supply continues to be a major challenge to limit circuit performance. To mitigate the impact of high-frequency voltage droop, a novel all-digital adaptive clock system is proposed. The adaptive clock system is composed of a droop detector and an adaptive clock generator, which directly stretch the clock period when the circuit suffers from the supply voltage droop. The droop detector circuit detects the VDD droop and the digital adaptive clock generator circuit selects the stretched clock to prevent timing-margin failures. The response time for droop detection and clock stretch can be as fast as one cycle. The whole scheme is used on a test circuit under SMIC 40nm CMOS process with a layout area of 900um*1100um. Post-layout simulation results demonstrate power reductions are 7％ at 1.1V and 15％ at 0.7V for a 10％ VDD droop, respectively.
Voltage droopAdaptive clock systemDroop detectorAdaptive clock generator
SHANG Xinchao、SHAN Weiwei、XIANG Yiming、WAN Liang、FAN Ao
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National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China
Spreadtrum Communications, Tianjin 300300, China
National Natural Science Foundation of ChinaNational Natural Science Foundation of ChinaNational 863 project
NETL
NSTL
万方数据
维普
