Design of Neural Network Hardware Accelerator based on Graph Convolution
At present,many applications need to be represented and processed by graph data.Graph data is irregular data located in non-Euclidean space.For the needs of graph data processing,graph convolutional neural network(GCN)came into being.The main processing steps of GCN are:aggregation,transformation and activation.In this paper,we adopt a heterogeneous pattern to accelerate the inference process of GCN.According to the characteristics of the data itself,the accelerator uses a systolic array to perform calculations to improve the data flow in the transfor-mation stage.In the aggregation stage,the load to be processed is divided into two types,which helps to improve the load imbalance phenomenon in the calculation process of the aggregation stage and shorten the calculation time to a certain extent.Finally,by evaluating the performance on the Xilinx Virtex UltraScale+VU37P HBM FPGA platform,this work achieves an average speedup of 389.19 × and 6.73 × relative to the CPU and GPU,respectively.
NETL
NSTL
万方数据
维普
