一种全尺寸MOS晶体管的俘获隧穿电流优化模型
An optimized model of trapped-tunneling current for full-scale MOS transistors
张瑜1
作者信息
摘要
针对当前的俘获隧穿电流模型中,对于不同器件尺寸只有统一的参数进行模型拟合,存在无法针对器件尺寸变化进行准确地模型拟合的问题.本文提出了在俘获隧穿电流模型的参数中,添加与器件全尺寸信息相关的方法,包括器件宽度方向,长度方向及小尺寸的系数对原有的漏电模型基础上进行优化,使得该优化的漏电模型能更好地反应器件特性实测数据,更好地解决了俘获隧穿电流更准确地表征器件特性的问题,这就提高了给电路设计者做仿真参考的准确性.
Abstract
Absrtact:For the current traditional trapped tunneling current model,there are only uniform parameters for model fitting for different device sizes,and there is a problem that the model cannot be accurately fitted for device size changes.In this paper,a method related to the full-size information of the device is proposed to be added to the parameters of the captured tunneling current model,including the width direction of the device,the length direction and the coefficient of small size to optimize the original leakage model,so that the optimized leakage model can better reflect the measured data of device characteristics,and better solve the problem of capturing tunneling current to characterize the characteristics of the device more accurately,which improves the simulation reference basis for circuit designers.
关键词
MOS晶体管/俘获隧穿电流/全尺寸/SPICE模型Key words
MOS transistor/captured tunneling current/full size/SPICE model引用本文复制引用
出版年
2024
NETL
NSTL
维普
万方数据