基于忆阻器混合CMOS的三模元余锁存器
A Triple Modular Redundancy Latch Based on Memristor Hybrid CMOS
段鑫沛 1肖平旦 2殷亚楠 1周昕杰 1刘兴强2
作者信息
- 1. 中国电子科技集团公司第五十八研究所
- 2. 湖南大学半导体学院(集成电路学院)
- 折叠
摘要
忆阻器的出现为后摩尔时代提供了 一个全新的方案以顺应更大的集成密度.为了研究其在数字电路中的应用,发挥潜在优势,本文首先介绍了忆阻器模型及比例逻辑构成的基本逻辑电路,随后提出了基于忆阻器混合CMOS的三模冗余D锁存器.所提出的三模冗余锁存器总体结构主要分为新型忆阻D锁存器的设计和三人表决器构建两个部分,能够在减小电路面积的同时实现电路可靠性的提升,为电路级抗辐射加固技术提供了一种新的思路.
Abstract
The appearance of memristor provides a new solution for the post-Moore's Law era to accommodate the greater integration density.In order to study its application in digital circuits and give full play to its potential advan-tages,this paper first introduces the memristor model and the basic logic circuit composed of proportional logic,and then proposes a three-mode redundant D latch based on the memristor hybrid CMOS.The proposed three-mode redundant latches are mainly divided into two parts:the design of novel memristor D latches and the construction of three-person voiders.It can reduce the area of the circuit and improve the reliability of the circuit at the same time,which provides a new idea for circuit-level radiation reinforcement technology.
关键词
忆阻器/CMOS/三模冗余/锁存器Key words
memristor/CMOS/triple modular redundancy/latch引用本文复制引用
基金项目
抗辐射应用技术创新中心创新基金(KFZC2021010202)
出版年
2024
NETL
NSTL
万方数据