一种基于FVF动态缓冲器的二阶噪声整形SAR ADC
A Second Order Passive Noise-Shaping SAR ADC based on FVF Dynamic Buffer
王炳煌1
作者信息
摘要
本文提出了一种高精度的二阶无源噪声整形逐次逼近型模数转换器(NSSARADC).首先,采用了一种通过动态浮动反向放大器(FIA)实现kT/C噪声消除的技术,随后结合差分结构的定制电容,实现更小的电容阵列面积的同时抑制了采样热噪声.最后,采用翻转电压跟随器(FVF)结构作为动态缓冲器提取残差电压,并通过电容堆叠的操作实现无源求和,对比较器噪声与量化噪声进行了二阶整形.该设计采用0.18 µm工艺实现,仿真表明,在1.8 V电源电压、8倍过采样率和2 MS/s的采样频率下,信号噪声失真比(SNDR)为88.57 dB,无杂散动态范围(SFDR)为99.09 dB,功耗仅为302μW.
Abstract
A high precision second order passive noise shaping successive approximation analog-to-digital converter(NS SAR ADC)is proposed in this paper.Firstly,a technique for kT/C noise cancellation via a dynamic floating reverse amplifier(FIA)was used,followed by a custom capacitor with a differential structure to achieve a smaller capacitor array area while suppressing sampling thermal noise.Finally,the residual voltage is extracted by using the flipped voltage follower(FVF)structure as a dynamic buffer,and the passive summation is realized by the capacitor stacking operation,and the comparator noise and quantization noise are shaped in the second order.This design is realized by 0.18 µ m process.The simulation results show that the signal-to-noise ratio(SNDR)is 88.57dB and the spury-free dynamic range(SFDR)is 99.09dB at 1.8V supply voltage,8x oversampling rate and 2MS/s sampling frequency.Power consumption is only 302 µ W.
关键词
模数转换器/噪声整形/kT/C噪声消除/FVF缓冲器Key words
analog-to-digital converter/noise shaping/kT/C noise cancellation/FVF buffer引用本文复制引用
出版年
2024
NETL
NSTL
维普
万方数据