The invention relates to the design of a ring VCO for a phase-locked loop
In this paper,based on 65nm standard CMOS technology,a circuit design of ring VCO for phase-locked loop(PLL)is proposed.Includes a ring oscillator and a buffer shaping circuit.The ring VCO has a four-stage delay unit,and the delay unit adopts Maneatis symmetrical load.Simulation on Cadence Spectre.The results show that when the power supply voltage is 1.8V,the frequency adjustment range is 0.277～1.33GHz,with good linearity.When the frequency offset is 1MHz,the phase noise is-92.46dBc/Hz@1MHz,which has good noise performance.The buffer shaping circuit converts the output waveform of the VCO to rail to rail voltage,resulting in a duty ratio equal to 50％and improved drive capability.The oscillators are stabilized at 400/500MHz respectively.
ring VCOphase-locked loopdelay elementthe comparator
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