一种高性能宽范围锁相环的设计与实现
Design and implementation of a high performance wide range phase-locked loop
郭风岐 1胡奕凡 1邱一武1
作者信息
摘要
采用CMOS工艺技术,设计了一款基于双环路滤波器的高性能、宽范围锁相环.该锁相环电路包括可调延迟的鉴频鉴相器、电荷泵、双环路有源滤波器、多频带的压控振荡器和可编程分频器模块.与无源滤波器结构相比,双环滤波的结构将滤波电容面积减小3/4,该锁相环整体版图面积为405µm× 480μm,经过仿真测试,锁相环能够提供的输出频率范围为140MHz～1.5GHz,整体功耗为6.85mW.设计的锁相环其流片测试结果显示:当输出频率为1.5GHz时,均方根抖动为8.92ps;当中心频率为820MHz时,均方根抖动为6.01ps,测试结果表明设计的这款锁相环输出频率能够满足使用需求.
Abstract
Using CMOS technology,a high performance,wide range phase-locked loop based on double loop filter is designed.The phase-locked loop circuit includes a frequency discriminator with adjustable delay,a charge pump,a double-loop active filter,a multiband voltage-controlled oscillator and a programmable frequency divider module.Compared with the passive filter structure,the double loop filter structure reduces the filter capacitance area by 3/4,the overall layout area of phase-locked loop is 405 µ m × 480 μ m.After simulation test,the output frequency range of phase-locked loop is 140MHz～1.5GHz,and the overall power consumption is 6.85mW.The flow plate test results of the designed phase-locked loop show that the RMS jitter is 8.92ps when the output frequency is 1.5GHz;When the center frequency is 820MHz,the RMS jitter is 6.01 ps.The test results show that the designed phase-locked loop output frequency can meet the requirements of use.
关键词
电荷泵锁相环/双环路滤波器/压控振荡器/可编程分频器Key words
charge pump phase-locked loop/double loop filter/voltage-controlled oscillator/programmable frequency divider引用本文复制引用
基金项目
抗辐射应用技术创新中心创新基金(KFZC2021010202)
出版年
2024
NETL
NSTL
万方数据